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1 of 16 051805 ds2740 high-precision coulomb counte r features ? 15-bit bidirectional current measurement (ds2740u) ? 1.56 v lsb and 51.2mv dynamic range ? 78 a lsb and 2.56a dynamic range with external 20m sense resistor (r sns ) ? 156 a lsb and 5.12a dynamic range with external 10m sense resistor (r sns ) ? 13-bit bidirectional current measurement (DS2740BU) ? 6.25 v lsb and 51.2mv dynamic range ? 312 a lsb and 2.56a dynamic range with external 20m sense resistor (r sns ) ? 625 a lsb and 5.12a dynamic range with external 10m sense resistor (r sns ) ? analog input filter (is1, is2) extends dynamic range for pulse-load applications ? current accumulation register resolution ? 6.25 vhr (both ds2740u and DS2740BU) ? 0.3125mahr with external 20m r sns ? 0.6250mahr with external 10m r sns ? dallas 1-wire ? interface ? unique 64-bit device address ? standard and overdrive timings (ovd) ? low power consumption: ? active current: 65 a max ? sleep current: 1 a max www.maxim-ic.com pin configuration pio v dd dq v ss is1 is2 o pin description ovd - 1-wire bus speed select pio - programmable i/o pin sns - sense resistor input is2 - current-sense input is1 - current-sense input v ss - device ground, current-sense resistor return dq - data input/output v dd - power-supply input (2.7v to 5.5v) max ( ds2740u , DS2740BU ) sns vd 6 8 1 7 2 3 5 4 see table 1 for ordering information. see table 2 for detailed pin descriptions. 1-wire is a registered trademark of dallas semiconductor.
ds2740 table 1. ordering information part marking description ds2740u d2740 15-bit current resolution, 8-pin max ds2740u+ d2740 (see note) 15-bit current resolution, lead-free 8-pin max ds2740u/t&r d2740 15-bit current resolution, 8-pin max, tape-and-reel ds2740u+t&r d2740 (see note) 15-bit current resolution, lead-free 8-pin max, tape- and-reel DS2740BU 2740b 13-bit current resolution, 8-pin max DS2740BU+ 2740b (see note) 13-bit current resolution, lead-free 8-pin max DS2740BU/t&r 2740b 13-bit current resolution, 8-pin max, tape-and-reel DS2740BU+t&r 2740b (see note) 13-bit current resolution, lead-free 8-pin max, tape- and-reel note: a ?+? will also be marked on th e package next to the pin 1 indicator. description the ds2740 provides high-precision current-flow measurement data to support battery-capacity monitoring in cost-sensitive applicat ions. current is measured bidirect ionally over a dynamic range of 15 bits (ds2740u) or 13 bits (DS2740BU) , with the net flow accumulated in a separate 16-bit register. through its 1-wire interface, the ds2740 allows the hos t system read/write access to status and current measurement registers. each device has a unique factor y-programmed 64-bit net address that allows it to be individually addressed by the host system, supporting multibattery slot operation. the interface can be operated with standard or overdrive timing. although the ds2740 is primarily intended for location on the host system, it is also suited for mounting in the battery pack. the ds2740 and fuelpack? al gorithms, along with host measurements of temperature and voltage, form a complete and accu rate solution for estimating remaining capacity. fuelpack is a trademark of dallas semiconductor. 2 of 16
ds2740 figure 1. block diagram 1-wire interface and address dq pio timebase current accumulated current status/control chip ground sns is2 v ss is1 15-bit + sign adc r is 10 k r is 10 k v dd r sns c f 3 of 16
ds2740 table 2. detailed pin descriptions pin symbol description ovd 1 1-wire bus speed control. input logic level selects the speed of the 1- wire bus. logic 1 selects overdrive (ovd) and logic 0 selects standard timing (std). on a multidrop bus, all devices must operate at same speed. pio 2 programmable i/o pin. programmed as input or output through internal registers. open-drain output sufficien t for led or vibrator activation. sns 3 current-sense resistor input is2 4 current-sense input. connected to sns through a 10k ? resistor to allow filtering of the current wa veform by an external capacitor. is1 5 current-sense input. connected to v ss through a 10k? resistor to allow filtering of the current waveform through an external capacitor. v ss 6 device ground, current-sense resistor return. connect directly to the negative terminal of the battery cell. dq 7 data i/o pin. operates bidirectionally with open-drain output driver. internal 1a pulldown aids in sensing pack removal and sleep-mode activation. v dd 8 power-supply input. connects to system voltage supply or positive terminal of battery cell. figure 2. application example ds2740 vdd vss dq pio data 2.7v to 5.5v system supply or battery pack positive connectio n to battery negative sns pio is1 is2 104 150 330 r sns 104 system gnd ovd * * * 5.6v zener recommended for esd protection when data or pio contacts exposed, such as a removable battery pack application 150 4 of 16
ds2740 5 of 16 power modes the ds2740 has two power modes: active and sleep . while in active mode, the ds2740 operates as a high-precision coulomb counter with current and accumulated current measurement blocks operating continuously and the resulting values updated in th e measurement registers. read and write access is allowed to all registers. pio pin is active. in sleep mode, the ds2740 operates in a low-power mode with no current measurement activity. serial access to current, accumulated current, and status/control registers is allowed if v dd > 2v. the ds2740 operating mode transitions from sleep to active when: 1) dq > v ih , and v dd > uv threshold, or 2) v dd rises from below uv threshold to above uv threshold. the ds2740 operating mode transition s from active to sleep when: 1) v dd falls to uv threshold, or 2) smod = 1 and dq < v il for 2s. current measurement in the active mode of operation, the ds2740 continually measures the cu rrent flow into and out of the battery by measuring the voltage drop acro ss a low-value current-sense resistor, r sns . to extend the input range for pulse-type load currents, the voltage signal can be filtered by adding a capacitor between the is1 and is2 pins. the external capacitor and two internal resistors form a lowpass filter at the input of the adc. the voltage-sense range at is1 and is2 is 51.2mv. the input converts peak signal amplitudes up to 102mv as long as the continuous or average si gnal level (post filter) does not exceed 51.2mv over the conversion cycle period. the adc samples the i nput differentially at is1 and is2 with an 18.6khz sample clock and updates the current register at th e completion of each conversion cycle. conversion times for each resolution option ar e listed in the tables below. two resolution options are available. figure 3 describes the current measurement register format and resolution for each option. ?s? indicates the sign bit(s). figure 3. current register format ds2740u : units: 1.5625 v/r sns , 15-bit + sign resolution, 3.5s conversion period. DS2740BU : units: 6.250 v/r sns , 13-bit + sign resolution, 0.875s conversion period. msb?address 0eh lsb?address 0fh s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb full-scale magnitude: 51.2mv
ds2740 6 of 16 current resolution (1 lsb) r sns part conversion time v is1 - v is2 20m 15m 10m 5m ds2740u 3.515s 1.5625 v 78.13 a 104.2 a 156.3 a 312.5 a DS2740BU 0.878s 6.250 v 312.5 a 416.7 a 625 a 1.250ma every 1024th conversion, the adc meas ures its input offset to facili tate offset correction. offset correction occurs approximately once per hour in the ds2740u a nd four times per hour in the DS2740BU. the resulting correction f actor is applied to the subsequent 1023 measurements. during the offset correction conversion, the adc does not meas ure the is1 to is2 signa l. a maximum error of 1/1024 in the accumulated current regi ster (acr) is possible, however, to reduce the error, the current measurement just prior to the offset conversion is displayed in the current register and is substituted for the dropped current measurement in the current accumu lation process. the typical error due to offset correction is much less than 1/1024. current accumulator current measurements are internally summed, or accumulated, at the completion of each conversion period with the results displayed in the acr. the accuracy of the acr is dependent on both the current measurement and the conversion timebase. the a cr has a range of 204.8mvh with a lsb of 6.25 vh . additional registers hold fractional results of each accumulation, however, these bits are not user accessible. read and write access is allowed to the acr. when ever the acr is written, fractional accumulation results are cleared. also, a write forces the adc to measure its offset and update the offset correction factor. the current measurement and accumulation begin with the second conversion following a write to the acr. figure 4 describes the acr address, format, and resolution. figure 4. current accumulator format msb?address 10h lsb?address 11h s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb units: 6.25 vh/r sns acr lsb r sns part update interval v is1 - v is2 20m 15m 10m 5m ds2740u 3.515s DS2740BU 0.878s 6.25 vh 312.5 ah 416.7 ah 625 ah 1.250mah
ds2740 7 of 16 acr range r sns part v is1 - v is2 20m 15m 10m 5m ds2740u DS2740BU 204.8mvh 10.24ah 13.65ah 20.48ah 40.96ah memory the ds2740 has memory space with registers for instru mentation, status, and control. when the msb of a two-byte register is read, both th e msb and lsb are latched and held for the duration of the read data command to prevent updates during the read and ensu re synchronization between the two register bytes. for consistent results, always read the msb and th e lsb of a two-byte register during the same read data command sequence. table 3. memory map address (hex) description read/write 00 reserved ? 01 status register r/w 02 to 07 reserved ? 08 special feature register r/w 09 to 0d reserved ? 0e current register msb r 0f current register lsb r 10 accumulated current register msb r/w 11 accumulated current register lsb r/w 12 to ff reserved ? status register the format of the status register is shown in figure 5. the f unction of each bit is desc ribed in detail in the following paragraphs. figure 5. status register format address 01 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x smod x rnaop x x x x smod ?sleep mode enable. a value of 1 allows the ds2740 to enter sleep mode when dq is low for 2s. a value of 0 disables dq rela ted transitions to sleep mode. th e power-up default of smod = 0. rnaop ?read net address opcode. a value of 0 in this bit sets the opcode for the read net address command to 33h, while a 1 sets the opcode to 39h. the power-up default of rnaop = 0. x ?reserved bits.
ds2740 8 of 16 special feature register the format of the special feature register is shown in figure 6. the function of each bit is described in detail in the following paragraphs. figure 6. special feature register format address 08 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x pio x x x x x x pio? pio pin sense and control. this bit is read and write enabled. writing a 0 to the pio bit enables the pio open-drain output driver, forc ing the pio pin low. writing a 1 to the pio bit disables the output driver, allowing the pio pin to be pu lled high or used as an input. r eading the pio bit returns the logic level forced on the pio pin. note that if pio is left floating, the weak pulldown brings the pin low. pio resets to a 1 at initial power up, when the ds2740 enters sleep mode, or dq low > t sleep (independent of the smod pin). x ?reserved bits. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. a multidrop bus is a 1-wire bus with multiple slaves. a single-drop bus has only one slave device. in all instances, the ds2740 is a slave device. the bus mast er is typically a microprocessor in the host system. the discussion of this bus system consists of four topics: 64-b it net address, hardware configuration, transaction sequence, and 1-wire signaling. 64-bit net address each ds2740 has a unique, factory-programmed 1-wire ne t address that is 64 bits in length. the first eight bits are the 1-wire family code (36h for ds2740) . the next 48 bits are a unique serial number. the last eight bits are a cyc lic redundancy check (crc) of the first 56 bits (see fi gure 7). the 64-bit net address and the 1-wire i/o circui try built into the de vice enable the ds2740 to communicate through the 1-wire protocol detailed in the 1-wire bus system section of this data sheet. figure 7. 1-wire net address format 8-bit crc 48-bit serial number 8-bit family code (36h ) msb lsb crc generation the ds2740 has an 8-bit crc stored in the most signifi cant byte of its 1-wire net address. to ensure error-free transmission of the address, the host syst em can compute a crc value from the first 56 bits of the address and compare it to the crc from the ds2740. the host system is responsible for verifying the crc value and taking action as a result. the ds2740 does not compare crc values and does not prevent a command sequence from proceeding as a result of a crc mismatch. proper use of the crc can result in a communication channel with a very high level of integrity.
ds2740 the crc can be generated by the host using a circuit consisting of a sh ift register and xor gates as shown in figure 8, or it can be generated in soft ware. additional information about the dallas 1-wire crc is available in application note 27, understanding and using cyclic redundancy checks with dallas semiconductor i button products . (this application note can be found on the maxim/dallas semiconductor website at www.maxim-ic.com.) in the circuit in figure 8, the shift re gister bits are initialized to 0. th en, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bi t of the serial number has been entered, the shift register contains the crc value. figure 8. 1-wire crc generation block diagram msb xor xor lsb xor input hardware configuration because the 1-wire bus has only a single line, it is im portant that each device on the bus be able to drive it at the appropriate time. to facilitate this, each devi ce attached to the 1-wire bus must connect to the bus with open-drain or tri- state output drivers. the ds2740 uses an op en-drain output driv er as part of the bidirectional interface circuitry shown in figure 9. if a bidirectional pin is not available on the bus master, separate output and input pins can be connected together. the 1-wire bus must have a pullup resistor at the bus-mas ter end of the bus. for short line lengths, the value of this resistor should be approximately 5k . the idle state for the 1-wire bus is high. if, for any reason, a bus transaction must be susp ended, the bus must be left in th e idle state to properly resume the transaction later. if the bus is left low for more than 120 s (16 s for overdrive speed), slave devices on the bus begin to interpret the low period as a rese t pulse, effectively terminating the transaction. the ds2740 can operate in two communication speed mode s, standard and overdrive. the speed mode is determined by the input logic level of the ovd pin with a logic 0 select ing standard speed and a logic 1 selecting overdrive speed. the ovd pi n must be at a stable logic leve l of 0 or 1 before initializing a transaction with a reset pulse. all 1-wire devi ces on a multinode bus must operate at the same communication speed for proper operation. 1-wire timing for both standard and overdrive speeds are listed in the electrical characteristic s: 1-wire interface tables. 9 of 16
ds2740 figure 9. 1-wire bus interface circuitry 10 of 16 transaction sequence the protocol for accessing the ds2740 thr ough the 1-wire port is as follows: ? initialization ? net address command ? function command ? transaction/data the sections that follow describe each of these steps in detail. all transactions of the 1-wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the bus master followed by a presence pulse simultaneously transmitted by the ds2740 and any other slaves on the bus. the presence pulse te lls the bus master that one or more devices are on the bus and ready to operate. for more details, see the 1-wire signaling section. net address commands once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following paragraphs. th e name of each net address command is followed by the 8-bit opcode for that command in square brackets. figure 10 presents a transaction flowchart of the net address commands. read net address [33h or 39h]. this command allows the bus mast er to read the ds2740?s 1-wire net address. this command can only be used if there is a single slave on the bus. if more than one slave is present, a data collision occurs when all slaves tr y to transmit at the same time (open drain produces a wired-and result). the rnaop bit in the status register selects the opcode for this command, with rnaop = 0 indicating 33h, a nd rnaop = 1 indicating 39h. match net address [55h]. this command allows the bus master to specifically address one ds2740 on the 1-wire bus. only the addressed ds2740 responds to any subsequent func tion command. all other slave devices ignore the function co mmand and wait for a reset pulse. th is command can be used with one or more slave devices on the bus. 1 a (typ) 100 mosfet tx rx rx tx rx = receive tx = transmit v pullup (2.0v to 5.5v) 4.7k bus master ds2740 1-wire port
ds2740 skip net address [cch]. this command saves time when ther e is only one ds2740 on the bus by allowing the bus master to issue a function command without specifying th e address of the slave. if more than one slave device is present on the bus, a subsequent function co mmand can cause a data collision when all slaves transmit data at the same time. search net address [f0h]. this command allows the bus master to use a process of elimination to identify the 1-wire net addresses of all slave devices on the bus. the search process involves the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this si mple three-step routine on each bit location of the net address. after one complete pass through all 64 bits, the bus master knows the address of one device. the remaining devices can then be identified on additiona l iterations of the process. see chapter 5 of the book of ds19xx i button ? standards for a comprehensive discussion of a net address search, including an actual example. (this publication can be found on the maxim/dallas semiconductor website at www.maxim- ic.com.) resume [a5h]. this command increases data throughput in multidrop environments where the ds2740 needs to be accessed several times. resume is sim ilar to the skip net address command in that the 64- bit net address does not have to be transmitted each time the ds2740 is accessed. after successfully executing a match net address command or search net address command, an internal flag is set in the ds2740. when the flag is set, the ds2740 can be repeatedly accessed through the resume command function. accessing another device on the bus clears the flag, thus prev enting two or more devices from simultaneously responding to the resume command function. function commands after successfully completing one of the net address commands, the bus master can access the features of the ds2740 with any of the function commands describe d in the following paragraphs and summarized in table 4. the name of each function is followed by the 8-bit opcode for that command in square brackets. read data [69h, xx]. this command reads data from the ds2740 starting at memory address xx. the lsb of the data in address xx is available to be r ead immediately after the msb of the address has been entered. because the address is automatically increm ented after the msb of each byte is received, the lsb of the data at address xx + 1 is available to be read immediately after the msb of the data at address xx. if the bus master continues to read beyond address ffh, the ds 2740 starts over at address 00h. addresses labeled ?reserved? in the memory map contain undefined da ta. the read data command can be terminated by the bus master with a reset pulse at any bit boundary. write data [6ch, xx]. this command writes data to the ds 2740 starting at memory address xx. the lsb of the data to be stored at address xx can be written immediately after th e msb of address has been entered. because the address is automatically incremen ted after the msb of each byte is written, the lsb to be stored at address xx + 1 can be written immedi ately after the msb to be stored at address xx. if the bus master continues to write beyond address ffh , the ds2740 starts over wr iting at address 00h. writes to read-only addresses and rese rved addresses are ignored. incomplete bytes are not written. see the memory section for more details. i button is a registered trademark of dallas semiconductor. 11 of 16
ds2740 figure 10. net address command flow chart master tx reset pulse ds2740 tx presence pulse master tx net address command 55h match 33h / 39h read f0h search cch skip ds2740 tx family code 1 byte ds2740 tx serial number 6 bytes ds2740 tx crc 1 byte master tx bit 0 bit 0 match ? master tx bit 1 ds2740 tx bit 0 ds2740 tx bit 0 master tx bit 0 bit 0 match ? ds2740 tx bit 1 ds2740 tx bit 1 master tx bit 1 bit 1 match ? bit 1 match ? master tx function command master tx bit 63 ds2740 tx bit 63 ds2740 tx bit 63 master tx bit 63 bit 63 match ? master tx function command yes no no no no yes yes yes no no no no yes yes yes yes no yes a5h resume yes no resume flag set ? master tx function command yes no set resume flag 12 of 16
ds2740 table 4. function commands command description command protocol bus state after command protocol bus data read data reads data from memory starting at address xx 69h, xx master rx up to 256 bytes of data write data writes data to memory starting at address xx 6ch, xx master tx up to 256 bytes of data 1-wire signaling the 1-wire bus requires strict signali ng protocols to ensure data integrity. the four protocols used by the ds2740 are as follows: the initialization sequence (rese t pulse followed by presence pulse), write 0, write 1, and read data. all of these types of signaling ex cept the presence pulse are initiated by the bus master. the initialization seque nce required to begin any communication with the ds2740 is shown in figure 11. a presence pulse following a reset pulse indicates that the ds2740 is ready to accept a net address command. the bus master transm its (tx) a reset pulse for t rstl . the bus master then releases the line and goes into receive mode (rx). the 1-wire bus line is then pulled high by the pullup resistor. after detecting the rising edge on th e dq pin, the ds2740 waits for t pdh and then transmits the presence pulse for t pdl . figure 11. 1-wire initialization sequence t r s tl t pdl t r s th t pdh pack+ pack- line type legend: bus m aster a c tive l o w ds2740 ac tive low resistor p ul lup both bus master and ds2740 active low dq write-time slots a write-time slot is initiated when the bus master pul ls the 1-wire bus from a logic-high (inactive) level to a logic-low level. there are two types of write-time slots: write 1 and write 0. all write-time slots must be t slot in duration with a 1 s minimum recovery time, t rec , between cycles. the ds2740 samples the 1-wire bus line between 15 s and 60 s (between 2 s and 6 s for overdrive speed) after the line falls. if the line is high when sampled, a write 1 occurs. if th e line is low when sample d, a write 0 occurs (see figure 12). for the bus master to ge nerate a write 1 time slot, the bus line must be pulled low and then released, allowing the line to be pulled high within 15 s (2 s for overdrive speed) af ter the start of the write-time slot. for the host to generate a write 0 tim e slot, the bus line must be pulled low and held low for the duration of the write-time slot. 13 of 16
ds2740 read-time slots a read-time slot is initiated when the bus master pul ls the 1-wire bus line from a logic-high level to a logic-low level. the bus master must keep the bus line low for at least 1 s and then release it to allow the ds2740 to present valid data. the bus ma ster can then sample the data t rdv from the start of the read- time slot. by the end of the read-time slot, the ds 2740 releases the bus line a nd allows it to be pulled high by the external pull up resistor. all read-time slots must be t slot in duration with a 1 s minimum recovery time, t rec , between cycles. see figure 12 for more information. figure 12. 1-wire write- and read-time slots 14 of 16
ds2740 15 of 16 absolute maxi mum ratings* voltage on v dd , dq, is1, is2, pio, relative to v ss -0.3v to +6v voltage on sns, relative to v ss -0.3v to +6v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/jedecj-std-020a * this is a stress rating only and fu nctional operation of th e device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operat ing conditions (2.7v v dd 5.5v; t a = 0 c to +70 c.) parameter symbol conditions min typ max units supply voltage v dd (note 1) 2.7 5.5 v data pin dq (note 1) -0.3 +5.5 v dc electrical characteristics (2.7v v dd 4.2v; t a = 0 c to +70 c.) parameter symbol conditions min typ max units 50 65 active current i active v dd = 5.5v 85 a v dd = 2.0v, dq = pio = v ss 0.6 1.0 sleep-mode current i sleep v dd = 4.2v, dq = pio = v ss 0.9 1.25 a undervoltage sleep threshold v uv 2.3 2.5 2.7 v ds2740u 1.5625 current resolution i lsb DS2740BU 6.25 v/r sns current full-scale magnitude i fs 51.2 mv/r sns ds2740u (note 2) -3 +1 +5 current measurement offset (auto calibrated) i oerr DS2740BU (note 2) -2 0 +2 lsb current gain error i gerr -1 +1 % of reading accumulated current resolution q ca 6.25 vh current sample clock frequency f samp 18.6 khz v dd = 3.5v at +25c -1 +1 timebase accuracy t err -4 +4 % input logic high: ovd v ih (note 1) v dd - 0.2v v input logic high: dq, pio v ih (note 1) 1.5 v input logic low: ovd v il (note 1) v ss + 0.2 v
ds2740 16 of 16 input logic low: dq, pio v il (note 1) 0.6 v output logic low: dq, pio v ol i ol = 4ma (note 1) 0.4 v dq, pio input pulldown current i pd v dd = 4.2v, v dq = 0.4v 0.5 a ovd input leakage il ovd pio bit = 1 -1 1 a dq capacitance c dq 50 pf dq low to sleep time t sleep (note 3) 2.0 2.4 s electrical characteristics: 1-w ire interface?standard speed (2.7v v dd 5.5v; t a = -20 c to +70 c.) parameter symbol min typ max units time slot t slot 60 120 s recovery time t rec 1 s write 0 low time t low0 60 120 s write 1 low time t low1 1 15 s read data valid t rdv 15 s reset time high t rsth 480 s reset time low t rstl 480 960 s presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s electrical characteristics: 1-w ire interface?overdrive speed (2.7v v dd 5.5v; t a = -20 c to +70 c.) parameter symbol min typ max units time slot t slot 6 16 s recovery time t rec 1 s write 0 low time t low0 6 16 s write 1 low time t low1 1 2 s read data valid t rdv 2 s reset time high t rsth 48 s reset time low t rstl 48 80 s presence detect high t pdh 2 6 s presence detect low t pdl 8 24 s note 1: all voltages are referenced to v ss . note 2: offset performance requires proper circuit layout design free of surface contaminants. note 3: the ds2740 enters the sleep mode 2.0s to 2.4s after dq goes low.

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